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S6B1741
128 SEG / 129 COM DRIVER & CONTROLLER FOR 4 GRAY SCALE STN LCD
May. 2002 Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
S6B1741 Specification Revision History Version 0.0 Preliminary specification Content Date May 24, 2002
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S6B1741
128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION ............................................................................................................................................ 1 FEATURES .................................................................................................................................................... 1 BLOCK DIAGRAM .......................................................................................................................................... 2 PAD CONFIGURATION.................................................................................................................................. 3 PAD CENTER COORDINTES ......................................................................................................................... 5 PIN DESCRIPTION ........................................................................................................................................ 9 Power supply .............................................................................................................................................. 9 LCD driver supply ........................................................................................................................................ 9 System control .......................................................................................................................................... 10 Microprocessor interface............................................................................................................................ 11 LCD driver outputs..................................................................................................................................... 12 FUNCTIONAL DESCRIPTION....................................................................................................................... 13 Microprocessor Interface............................................................................................................................ 13 Display Data RAM (DDRAM) ...................................................................................................................... 18 LCD Display Circuits.................................................................................................................................. 21 LCD Driver Circuit...................................................................................................................................... 26 Power supply circuits ................................................................................................................................. 29 Reference Circuit Examples ....................................................................................................................... 34 Reset Circuit ............................................................................................................................................. 36 INSTRUCTION DESCRIPTION ..................................................................................................................... 38 SPECIFICATIONS ........................................................................................................................................ 62 Absolute Maximum Ratings ........................................................................................................................ 62 DC Characteristics..................................................................................................................................... 63 AC Characteristics..................................................................................................................................... 66 REFERENCE APPLICATIONS ...................................................................................................................... 72 Microprocessor Interface............................................................................................................................ 72 Connections between S6B1741 and LCD Panel .......................................................................................... 74
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
INTRODUCTION
The S6B1741 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. It contains 128 segment and 129 common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI) or 8-bit parallel display data and stores in an on-chip display data RAM of 128 x 129 x 2 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
4-level (White, Light Gray, Dark Gray, Black) Gray Scale Display with PWM and FRC Methods DDRAM data [2n: 2n+1] 00 01 10 Dark gray 11 Dark
Gray scale White Light gray (Accessible column address, n = 0, 1, 2, ......, 125, 126, 127) Driver Output Circuits -- 128 segment outputs/129 common outputs Applicable Duty Ratios Duty Ratio 1/16 - 1/128 (ICON disabled) 1/17 - 1/129 (ICON enabled) Various partial displays Partial window moving & data scrolling Applicable LCD Bias 1/5 to 1/12
Maximum Display Area 129 x 128
-- --
On-chip Display Data RAM -- Capacity: 129 x 128 x 2 = 33,024bits Microprocessor Interface -- 8-bit parallel bi-directional interface with 6800-series or 8080-series -- SPI (serial peripheral interface) available (only write operation) On-chip Low Power Analog Circuit -- On-chip oscillator circuit -- Voltage converter (x3, x4, x5 or x6) -- Voltage regulator (temperature coefficient: -0.125%/C, or external input) -- On-chip electronic contrast control function (64 steps) -- Voltage follower (LCD bias: 1/5 to 1/12) Operating Voltage Range -- Supply voltage (V DD): 1.8 to 3.3V -- LCD driving voltage (V LCD = V0 - VSS): 4.0 to 15.0 V Low Power Consumption -- 300 A Max. (operation) -- 2 A Max. (sleep mode) Package Type -- Slim chip for TCP
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
COM1 COM127 COM126 : SEG127 SEG126 SEG125
COM1 COM0 COMS
SEG2 SEG1 SEG0
:
VDD V0 V1 V2 V3 V4 VSS
128 Segment Driver Circuit
129 Common Driver Circuit
Display Latch Circuit
FRC/PWM Function Circuit
V/F Circuit V0 VR INTRS VEXT REF VOUT C1C1+ C2C2+ C3+ C4+ C5+ VCI Page Address Circuit V/R Circuit I/O Buffer
DisplayDataRAM 129X128X2 =33,024 Bits
Common Output Controller Circuit
Line Address Circuit
Oscillator /Display Timing Control
OSC1
Column Address Circuit
V/C Circuit Status Register BUS Holder Internal Power Supply MPU Interface (Parallel & Serial) Instruction Register Instruction Decoder
Figure 1. Block Diagram
RESETB
PS0 PS1
RS CSB
E_RD
RW_WR
DB7(SID)
DB6(SCLK)
DB5
DB4
DB3
DB2
DB1
DB0
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
PAD CONFIGURATION
374 375
181 180
Y
X (0,0)
S6B0741
143 1
411
144
PAD
Figure 2. S6B1741 Chip Configuration
Table 1. S6B1741 Pad Dimensions Items Chip size Pad pitch 1-143 144-178, 183-372, 377-411 179-182, 373-376 Bumped pad size 1-143 145 -178, 377-410 183-372 144, 179-180, 375-376, 411 181-182, 373-374 Bumped pad height ALL PAD 42 70 34 70 62 14(Typ.) Pad No. X 10580 70 52 80 92 34 70 62 70 Size Y 2520 m Unit
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
COG Align Key Coordinate
30m 30m 30m 30m 30m 30m 30m 30m 30m
ILB Align Key Coordinate(with Gold Bump*)
42m x (-4607 , +704.5) 42m 60m 108m 108m 108m 42m
(+4527 , +624.5) x
x
108m
30m
(-4690 , -515)
42m
(+4770 , -580)
x
* When designing electrode pattern must be prohibited on this area (ILB Align Key). If electrode pattern is used for routing over this area, it can be happened pattern-short through bumped pattern on ILB Align Key.
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates [Unit: m] Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Coordinate X -4970 -4900 -4830 -4760 -4690 -4620 -4550 -4480 -4410 -4340 -4270 -4200 -4130 -4060 -3990 -3920 -3850 -3780 -3710 -3640 -3570 -3500 -3430 -3360 -3290 -3220 -3150 -3080 -3010 -2940 -2870 -2800 -2730 -2660 Y -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 Pad No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VDD TEST1 VSS PS0 VDD PS1 VSS CSB RESETB VDD Coordinate X -2590 -2520 -2450 -2380 -2310 -2240 -2170 -2100 -2030 -1960 -1890 -1820 -1750 -1680 -1610 -1540 -1470 -1400 -1330 -1260 -1190 -1120 -1050 -980 -910 -840 -770 -700 -630 -560 -490 -420 -350 -280 Y -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 Pad No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Pad Name RS RW_WR VSS E_RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VDD VDD VDD VCI VCI VSS VSS VSS VSS VSS VSS VSS VOUT VOUT C5+ C5+ C3+ C3+ Coordinate X -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1260 1330 1400 1470 1540 1610 1680 1750 1820 1890 1960 2030 2100 Y -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Table 2. Pad Center Coordinates (Continued) [Unit: m] Pad No. 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 Pad Name C1C1C1+ C1+ C2+ C2+ C2C2C4+ C4+ VDD VDD REF VSS VEXT VDD INTRS VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 VR VR VSS VSS VDD OSC1 DUMMY DUMMY Coordinate X 2170 2240 2310 2380 2450 2520 2590 2660 2730 2800 2870 2940 3010 3080 3150 3220 3290 3360 3430 3500 3570 3640 3710 3780 3850 3920 3990 4060 4130 4200 4270 4340 4410 4480 4550 4620 4690 Y -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 Pad No. 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 Coordinate X 4760 4830 4900 4970 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 Y -1145 -1145 -1145 -1145 -964 -898 -846 -794 -742 -690 -638 -586 -534 -482 -430 -378 -326 -274 -222 -170 -118 -66 -14 38 90 142 194 246 298 350 402 454 506 558 610 662 714 Pad No. 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 Pad Name COM31 COM30 DUMMY DUMMY DUMMY DUMMY COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS Coordinate X 5166 5166 5166 5166 5060 4980 4914 4862 4810 4758 4706 4654 4602 4550 4498 4446 4394 4342 4290 4238 4186 4134 4082 4030 3978 3926 3874 3822 3770 3718 3666 3614 3562 3510 3458 3406 3354 Y 766 818 884 964 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
Table 2. Pad Center Coordinates (Continued) [Unit: m] Pad No. 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 Pad Name SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Coordinate X 3302 3250 3198 3146 3094 3042 2990 2938 2886 2834 2782 2730 2678 2626 2574 2522 2470 2418 2366 2314 2262 2210 2158 2106 2054 2002 1950 1898 1846 1794 1742 1690 1638 1586 1534 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 Pad No. 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 Pad Name SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 Coordinate X 1482 1430 1378 1326 1274 1222 1170 1118 1066 1014 962 910 858 806 754 702 650 598 546 494 442 390 338 286 234 182 130 78 26 -26 -78 -130 -182 -234 -286 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 Pad No. 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 Pad Name SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 Coordinate X -338 -390 -442 -494 -546 -598 -650 -702 -754 -806 -858 -910 -962 -1014 -1066 -1118 -1170 -1222 -1274 -1326 -1378 -1430 -1482 -1534 -1586 -1638 -1690 -1742 -1794 -1846 -1898 -1950 -2002 -2054 -2106 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Table 2. Pad Center Coordinates (Continued) [Unit: m] Pad No. 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 Pad Name SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 Coordinate X -2158 -2210 -2262 -2314 -2366 -2418 -2470 -2522 -2574 -2626 -2678 -2730 -2782 -2834 -2886 -2938 -2990 -3042 -3094 -3146 -3198 -3250 -3302 -3354 -3406 -3458 -3510 -3562 -3614 -3666 -3718 -3770 -3822 -3874 -3926 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 Pad No. 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 Pad Name COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 DUMMY DUMMY DUMMY DUMMY COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 Coordinate X -3978 -4030 -4082 -4134 -4186 -4238 -4290 -4342 -4394 -4446 -4498 -4550 -4602 -4654 -4706 -4758 -4810 -4862 -4914 -4980 -5060 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 964 884 818 766 714 662 610 558 506 454 402 350 298 246 Pad No. 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 Pad Name COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COMS1 DUMMY Coordinate X -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 Y 194 142 90 38 -14 -66 -118 -170 -222 -274 -326 -378 -430 -482 -534 -586 -638 -690 -742 -794 -846 -898 -964
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
PIN DESCRIPTION
POWER SUPPLY Table 3. Power Supply Pin Description Name VDD VSS V0 V1 V2 V3 V4 I/O Supply Supply I/O Power supply Ground LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias
NOTE: N = 5 to 12
Description
V1 (N-1)/N x V0
V2 (N-2)/N x V0
V3 (2/N) x V0
V4 (1/N) x V0
LCD DRIVER SUPPLY Table 4. LCD Driver Supply Pin Description Name C1C1+ C2C2+ C3+ C4+ C5+ VOUT VCl VR I/O O O O O O O O I/O I I Description Capacitor 1 negative connection pin for voltage converter Capacitor 1 positive connection pin for voltage converter Capacitor 2 negative connection pin for voltage converter Capacitor 2 positive connection pin for voltage converter Capacitor 3 positive connection pin for voltage converter Capacitor 4 positive connection pin for voltage converter Capacitor 5 positive connection pin for voltage converter Voltage converter input/output pin Voltage converter input voltage pin V0 voltage adjustment pin It is valid only when on-chip resistors are not used (INTRS = "L") When using internal resistors (INTRS = "H"), open this pin Selects the external VREF voltage via the VEXT pin - REF = "H": using the internal VREF - REF = "L": using the external VREF Externally input reference voltage (VREF) for the internal voltage regulator It is valid only when REF is "L" When using internal voltage regulator, connect to VDD, VSS or open this pin When using internal clock oscillator, connect a resistor between OSC1 and VDD.
REF
I
VEXT
I
OSC1
I
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
SYSTEM CONTROL Table 5. System Control Pin Description Name INTRS I/O I Description Internal resistor select pin This pin selects the resistors for adjusting V0 voltage level - INTRS = "H": use the internal resistors. - INTRS = "L": use the external resistors. VR pin and external resistive divider control V0 voltage Test pins Do not use this pin. - TEST1: Open this pin.
TEST1
O
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S6B1741
MICROPROCESSOR INTERFACE Table 6. Microprocessor Interface Pin Description Name RESETB PS0 I/O I I Description Reset input pin When RESETB is "L", initialization is executed. Parallel/Serial data input select input PS0 H L Interface mode Parallel Serial Data/instruction RS RS or None Data DB0 to DB7 SID (DB7) Read/Write E_RD RW_WR Write only Serial clock - SCLK (DB6)
NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either "H" or "L".
PS1
I
Microprocessor interface select input pin - PS0 = "H", PS1= "H": 6800-series parallel MPU interface - PS0 = "H", PS1= "L": 8080-series parallel MPU interface - PS0 = "L", PS1 = "H": 4 pin-SPI MPU interface - PS0 = "L", PS1 = "L": 3 pin-SPI MPU interface Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin - RS = "H": DB0 to DB7 are display data Read/Write execution control pin C68 H L MPU type 6800-series 8080-series RW_WR RW /WR Description Read/Write control input pin - RW = "H": read - RW = "L" : write Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal. Description Read/Write control input pin - RW = "H": When E is "H", DB0 to DB7 are in an output status. - RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal. L 8080-series /RD Read enable clock input pin When /RD is "L", DB0 to DB7 are in an output status. - RS = "L": DB0 to DB7 are control data
CSB
I
RS RW_WR
I I
E_RD
I
Read/Write execution control pin PS1 H MPU Type 6800-series E_RD E
DB0 to DB7
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS0 = "L"); - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance.
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS Table 7. LCD Driver Output Pin Description Name SEG0SEG127 I/O O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data H H L L Power save mode COM0-C OM127 O M (Internal) H L H L Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data H H L L Power save mode M (Internal) H L H L Common driver output voltage VSS V0 V1 V4 VSS
COMS (COMS1)
NOTE:
O
Common output for the icons The output signals of two pins are same. When not used, these pins should be left open.
DUMMY -- These pins should be opened (floated).
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The S6B1741 can interface with an MPU when CSB is "L". When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel/Serial Interface S6B1741 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table 8. Table 8. Parallel/Serial Interface Mode Type CSB Serial PS1 H L H L CSB CSB CSB PS0 H L Interface mode 6800-series MPU mode 8080-series MPU mode 4-pin SPI mode 3-pin SPI mode
Parallel Interface (PS0 = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in Table 10. Table 9. Microprocessor Selection for Parallel Interface PS1 H L CSB CSB CSB RS RS RS E_RD E /RD RW_WR RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Table 10. Parallel Data Transfer Common RS H H L L
NOTE:
6800-series E_RD (E) H H H H RW_WR (RW) H L H L
8080-series E_RD (/RD) L H L H RW_WR (/WR) H L H L
Description
Display data read out Display data write Register status read Writes to internal register (instruction)
When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at RS, RW_WR as in case of 6800-series mode.
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
CSB RS RW E DB Command Write Data Write Status Read Data Read
Figure 3. 6800-Series MPU Interface protocol (PS0="H", PS1="H")
CSB RS /WR /RD DB Command Write Data Write Status Read Data Read
Figure 4. 8080-Series MPU Interface Protocol (PS0="H", PS1="L")
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S6B1741
Serial Interface (PS0 = "L") When the S6B1741 is active(CSB="L"), serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select(RS) Pin, based on the setting of PS1. When the RS pin is used (PS1 = "H"), data is display data when RS is high, and command data when RS is low. When RS is not used (PS1 = "L"), the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data Direction command(11101000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are send, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. Serial mode 4-Pin SPI mode 3-Pin SPI mode PS0 L L PS1 H L CSB CSB CSB RS Used Not used
4-pin SPI Mode (PS0 = "L" , PS1 = "H")
CSB
SID SCLK RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
Figure 5. 4-pin SPI Timing (RS is used)
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
3-pin SPI Mode (PS0 = "L" , PS1 = "L") To write data to the DDRAM, send Data Direction Command in 3-pin SPI mode. Data is latched at the rising edge of SCLK. And the DDRAM column address pointer will be increased by one automatically.
CSB
0 SCLK 3 Byte(1) SID Page MSB LSB
23 0 1
78
15 0
829 830 831
2 Byte(2) DDC No. of DATA
104 Byte Data In
(1) Set Page and Column Address. Set Page Address : 1 0 1 1 P3 P2 P1 P0 Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4 Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0 (2)Set DDC(Data Direction Command) and No. of Data Bytes. Set Data Direction Command ( For SPI mode Only): 11101000 Set No. of Data Bytes : D7 D6 D5 D4 D3 D2 D1 D0 (3) This figure is example for 104 Data bytes to be transfered.
Figure 6. 3-pin SPI Timing (RS is not used) This command is used in 3-pin SPI mode only. It will be two continuous commands, the first byte controls the data direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first.
NOTE: In spite of transmission of data, if CSB will be disable, state terminates abnormally. Next state is initialized.
Busy Flag The Busy Flag indicates whether the S6B1741 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
Data Transfer The S6B1741 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 7. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signals RS /WR DB0 to DB7 N D(N) D(N+1) D(N+2) D(N+3)
Internal signals /WR BUS Holder Column Address N N D(N) D(N+1) N+1 D(N+2) N+2 D(N+3) N+3
Figure 7. Write Timing
MPU signals RS /WR /RD DB0 to DB7 N Dummy Internal signals /WR /RD BUS Holder Column Address N N D(N) N+1 D(N+1) N+2 D(N+2) N+3 D(N) D(N+1) D(N+2)
Figure 8. Read Timing
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 129-row (17 page by 8 bits) by 128-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. Page Address Circuit This circuit is for providing a Page Address to Display Data RAM shown in Figure 10. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 10. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons.
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
Column Address Circuit Column Address Circuit has a 8-bit preset counter that provides Column Address to the Display Data RAM as shown in figure 10. When set Column Address MSB/LSB instruction is issued, 7-bit [Y7:Y1] are set and lowest bit, Y0 is set to "0". Since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 80H. It is unlocked if a column address is set again by set Column Address MSB/LSB instruction. And the column address counter is independent of page address register. ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following Figure 9.
SEG OUTPUT Column Address [Y7:Y1] Internal Column Address [Y7:Y0] Display Data (ADC=0) LCD Panel Display
SEG0 00H
SEG1 01H
SEG2 02H
SEG3 03H
... ... ... ...
SEG124 SEG125 SEG126 SEG127 7CH 7DH 7EH 7FH
00 01 02 03 04 05 06 07 HEX HEX HEX HEX HEX HEX HEX HEX
... ... ... ... ... ...
F8 F9 FA FB FC FD FE FF HEX HEX HEX HEX HEX HEX HEX HEX
1
1
1
0
0
0
0
1
1
0
1
1
0
0
0
1
Display Data (ADC = 1) LCD Panel Display
0
1
0
0
1
1
1
0
... ... ... ...
0
1
0
0
1
0
1
1
Figure 9. The Relationship between the Column Address and the Segment Outputs Segment Control Circuit This circuit controls the display data by the display ON/OFF, reverse display ON/OFF and entire display ON/OFF instructions without changing the data in the display data RAM.
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
DB4
DB3
Page Address DB2
DB1
DB0
Data DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 7A 7B 7C 7D 7E 7F 05 04 03 02 01 00 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COMS
0
0
0
0
0
Page0
End = 07H
Start = 08H 1/129 Duty 1/121 Duty
0
0
0
0
1
Page1
0
0
0
1
0
Page2
0
0
0
1
1
Page3
DB0 DB1 DB2 DB3 Page12 0 1 1 0 0 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 Page13 0 1 1 0 1 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 0 1 1 1 Page14 0 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 0 1 1 1 1 Page15 DB4 DB5 DB6 DB7 DB0 Page16 (*) 1 0 0 0 0 (*)When ICON control register is set to "1", page address is set to "16", and user can write data for display icons. Column Address [Y7:Y1] ADC=0 ADC=1 7F 00 01 02 03 04 05 7E 7D 7C 7B 7A SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 -------------
Initial Start Line Address = 08H
LCD Segement Output
Figure 10. Display Data RAM Map
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
LCD DISPLAY CIRCUITS FRC (Frame Rate Control) and PWM (Pulse Width Modulation) Function Circuit The S6B1741 incorporates an FRC function and a PWM function circuit to display a 4-level gray scale. The FRC function and PWM utilize liquid crystal characteristics whose transmission is changed by an effective value of applied voltage. The S6B1741 provides four 4-bit palette-registers to assign the desired gray level. These registers are set by the instructions and the RESETB. -- Gray Scale Table of 4 FRC (Frame Rate Control) Gray scale level White MSB (DB7 to DB4) 2nd FR (FR2) 4th FR (FR4) Light gray 2nd FR (FR2) 4th FR (FR4) Dark gray Black 2nd FR (FR2) 4th FR (FR4) 2nd FR (FR2) 4th FR (FR4) -- Gray Scale Table of 3 FRC (Frame Rate Control) Gray scale level White MSB (DB7 to DB4) 2nd FR (FR2) xxxx Light gray 2nd FR (FR2) xxxx Dark gray 2nd FR (FR2) xxxx Black 2nd FR (FR2) xxxx LSB (DB3 to DB0) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) LSB (DB3 to DB0) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3)
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
--
Gray Scale Table of 15 PWM (Pulse Width Modulation) Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 4-bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM (on width) 0 (0/15) 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 1 (15/15) Darker Note Brighter
--
Gray Scale Table of 12 PWM (Pulse Width Modulation) Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 4-bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM (on width) 0 (0/12) 1/12 2/12 3/12 4/12 5/12 6/12 7/12 8/12 9/12 10/12 11/12 1 (12/12) 0/12 0/12 0/12 Darker This area is selected to OFF level (0/12 level) Note Brighter
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
--
Gray Scale Table of 9 PWM (Pulse Width Modulation) Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 4-bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM (on width) 0 (0/9) 1/9 2/9 3/9 4/9 5/9 6/9 7/9 8/9 1 (9/9) 0/9 0/9 0/9 0/9 0/9 0/9 Darker
This area is selected to OFF level (0/9 level)
Note Brighter
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Oscillator This is on-chip Oscillator with external resistor. Its frequency is controlled by external resistor between OSC1 and VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL(internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 128-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 11.
127 128 1
2
3
4
5
6
7
8
9 10 11 12
121 122 123 124 125 126 127 128 1
2
3
4
5
6
CL(Internal) FR(Internal) M(Internal)
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 11. 2-frame AC Driving Waveform (Duty Ratio = 1/128)
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
127 128 1
2
3
4
5
6
7
8
9 10 11 12
121 122 123 124 125 126 127 128 1
2
3
4
5
6
CL(Internal) FR(Internal) M(Internal)
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 12. N-Line Inversion Driving Waveform (N = 5, Duty Ratio = 1/128)
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER CIRCUIT This driver circuit is configured by 129-channel common drivers and 128-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD
M
VSS V0 V1 V2
COM0
V3 V4 VSS V0 V1 V2
COM1
V3 V4 VSS V0 V1 V2
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
COM2
V3 V4 VSS V0 V1 V2
SEG0
V3 V4 VSS V0 V1 V2
SEG1
V3 V4 VSS V0 V1 V2
SEG2
V3 V4 VSS
Figure 13. Segment and Common Timing
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
Partial Display on LCD The S6B1741 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages
-------------------------
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Figure 14. Reference Example for Partial Display
-------------------------
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Figure 15. Partial Display (Partial Display Duty = 16, Initial COM0 = 0)
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
-- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23
Figure 16. Moving Display (Partial Display Duty = 16, Initial COM0 = 8)
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
POWER SUPPLY CIRCUITS The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 11 shows the referenced combinations in using Power Supply circuits. Table 11. Recommended Power Supply Combinations User setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power ontrol (VC VR VF) 111 011 V/C circuits ON OFF V/R circuits ON ON V/F circuits ON ON VOUT Open External input V0 Open Open V1 to V4 Open Open
001 000
OFF OFF
OFF OFF
ON OFF
Open Open
External input External input
Open External input
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Voltage Converter Circuits These circuits boost up the electric potential between VCI and VSS to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by "Set DC-DC Step-up" instruction. When the higher level is selected by instruction, VOUT voltage is not valid. [C1 = 1.0 to 4.7 F]
VSS VOUT C5+ C3+ C1C1+ C2+ C2C4+
+
VSS C1 VOUT C5+ C3+
+
C1
+ + + -
VOUT = 4 x VCI C1 C1 VCI
+ + -
VOUT = 3 x VCI C1
C1C1+
C1
VCI
C2+ C2-
C1
VSS
C4+
VSS
Figure 17. Three Times Boosting Circuit
Figure 18. Four Times Boosting Circuit
VSS VOUT C5+ C3+ C1C1+ C2+ C2C4+
+
VSS C1 VOUT VOUT = 5 x VCI C5+ C3+ C1 C1 VCI C1 C2C1 VSS C4+ C1C1+ C2+
+
C1
VOUT = 6 x VCI
+ + + +
+ C1 + C1 C1 + + + VCI C1 C1 VSS
Figure 19. Five Times Boosting Circuit
Figure 20. Six Times Boosting Circuit
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 19, it is necessary to be applied internally or externally. For the Eq.1, we determine V0 by Ra, Rb and V EV . The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq.2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25C is shown in Table 12. V0 = (1 + Rb ) x VEV [V] ------ (Eq.1) Ra (63 -) ) x VREF [V] ------ (Eq.2) 210 Table 12 . VREF Voltage at Ta = 25C REF 1 0 Temp. coefficient -0.125%/C External input VREF [ V ] 2.1 VEXT
VEV = (1 -
VOUT
+ V0 VEV Rb
VR
Ra
Vss
GND
Figure 21. Internal Voltage Regulator Circuit
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 13. Internal Rb/Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 000 1 + (Rb/Ra) 2.3 001 3.0 010 3.7 011 4.4 100 5.1 101 5.8 110 6.5 111 7.2
Figure 22 Shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb/Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C.
16.00 (1, 1, 1) 14.00 12.00 V0 voltage [V] 10.00 8.00 6.00 4.00 2.00 0.00 0 8 16 24 32 40 48 56 63 (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0)
Electronic Volume Register (0 to 63)
Figure 22. Electronic Volume Level (Temp. Coefficient = -0.125%/ C)
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements LCD driver voltage, V0 = 10V 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) Maximum current flowing Ra, Rb = 1 A From Eq. 1 Rb 10 = (1 + ) x VEV [V] ------ (Eq.3) Ra From Eq. 2 (63-32) VEV = (1 ) x 2.1 = 1.79 [V] ------ (Eq.4) 210 From requirement 3. 10 = 1 [A] ------ (Eq.5) Ra + Rb From equations Eq.3, 4 and 5 Ra = 1.79 [M] Rb = 8.21 [M] Table 14 Shows the Range of V0 depending on the above Requirements. Table 14. The Range of V0 Electronic volume level 0 V0 8.21 ....... ....... 32 10.00 ....... ....... 63 11.73
Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 15 shows the relationship between V1 to V4 level and each duty ratio. Table 15. The Relationship between V1 to V4 Level and Each Duty Ratio LCD bias 1/N V1 (N-1)/N x V0 V2 (N-2)/N x V0 V3 2/N x V0 V4 1/N x V0 Remarks N = 5 to 12
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
REFERENCE CIRCUIT EXAMPLES [C1 = 1.0 to 4.7 [F], C2 = 0.47 to 2.0 [F]]
When using internal regulator resistors VDD INTRS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR C2 C2 C2 C2 C2 VSS + + + + + V0 V1 V2 V3 V4 VSS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR Rb C2 C2 C2 C2 C2 + + + + + V0 V1 V2 V3 V4 INTRS VSS When not using internal regulator resistors
C1
C1 C1 C1 C1
C1
C1 C1 C1 C1
C1
C1 Ra
Figure 23. When Using all LCD Power Circuits (6-Time V/C: ON, V/R: ON, V/F: ON) [C2 = 0.47 to 2.0 [F]]
When using internal regulator resistors VDD INTRS External Power Supply VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4 VSS External Power Supply VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR C2 C2 C2 C2 C2 + + + + + C2 C2 C2 C2 C2 + + + + + Rb V0 V1 V2 V3 V4 INTRS VSS When not using internal regulator resistors
Ra
VSS
Figure 24. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON)
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
[C2 = 0.47 to 2.0 [F]]
VDD INTRS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4 VSS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4 VDD INTRS
External Power Supply
C2 C2 C2 C2 C2 VSS
-
+ + + + +
External Power Supply
Figure 25. When Using some LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: ON)
Figure 26. When Not Using any Internal LCD Power Supply Circuits (V/C: OFF, V/R: OFF, V/F: OFF)
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
RESET CIRCUIT Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", following procedure is occurred. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Page address: 0 Column address: 0 Read-modify-write: OFF Display ON/OFF: OFF Initial display line: 0 (first) Initial COM0 register: 0 (COM0) Partial display duty ratio: 1/128 Reverse display ON/OFF: OFF (normal) N-line inversion register: 0 (disable) Entire Display ON/OFF: OFF ICON Control register ON/OFF: OFF (ICON disable) Power control register (VC, VR, VF) = (0, 0, 0) DC-DC converter circuit = (0, 0) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 LCD bias ratio: 1/12 COM Scan Direction: 0 ADC Select: 0 Oscillator: OFF Power Save Mode: Release Display Data Length register: 0 (for SPI mode) White mode set: OFF White palette register (WG3, WG2, WG1, WG0) = (0, 0, 0, 0) Light gray mode set: OFF Light gray palette register (LG3, LG2, LG1, LG0) = (0, 0, 0, 0) Dark gray mode set: OFF Dark gray palette register (DG3, DG2, DG1, DG0) = (1, 1, 1, 1) Black mode set: OFF Black palette register (BG3, BG2, BG1, BG0) = (1, 1, 1, 1) FRC, PWM mode: 4FRC, 9PWM
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
When RESET instruction is issued, following procedure is occurred. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Page address: 0 Column address: 0 Read-modify-write: OFF Initial display line: 0 (First) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 Display Data Length register: 0 (for SPI mode) White mode set: OFF White palette register (WG3, WG2, WG1, WG0) = (0, 0, 0, 0) Light gray mode set: OFF Light gray palette register (LG3, LG2, LG1, LG0) = (0, 0, 0, 0) Dark gray mode set: OFF Dark gray palette register (DG3, DG2, DG1, DG0) = (1, 1, 1, 1) Black mode set: OFF Black palette register (BG3, BG2, BG1, BG0) = (1, 1, 1, 1) FRC, PWM mode: 4FRC, 9PWM
While RESETB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 16 Instruction Table
Instruction Read display data Write display data Read status ICON control register ON/OFF RS 1 1 0 0 RW 1 0 1 0
BUSY ON/OFF
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Description Read data from DDRAM Write data into DDRAM
Read data Write data RS E 1 MF2 0 MF1 0 MF0 0 DS1 1 DS0
Read the internal status
1
0
ICON ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16
Set page address Set column address MSB Set column address LSB Set modify-read Reset modify-read Display ON/OFF
0 0 0 0 0 0
0 0 0 0 0 0
1 0 0 1 1 1
0 0 0 1 1 0
1 0 0 1 1 1
1 1 0 0 0 0
P3 0 Y4 0 1 1
P2 Y7 Y3 0 1 1
P1 Y6 Y2 0 1 1 x S1 x C1 x D1 x N1 0 1
P0 Y5 Y1 0 0
Set page address Set column address MSB Set column address LSB Set modify-read mode release modify-read mode
DON DON=0: display OFF DON=1: display ON x S0 x C0 x D0 x N0 0 REV 2-byte instruction to specify the initial display line to realize vertical scrolling 2-byte instruction to specify the initial COM0 to realize window scrolling 2-byte instruction to set partial display duty ratio 2-byte instruction to set N-line inversion register Release N-line Inversion mode REV=0: normal display, REV=1: reverse display
Set initial display line register
0
0
0 x 0 x 0 D7 0 x 1 1
1
0
0
0
0
0 Set initial COM0 register 0
0 0
S6 1
S5 0
S4 0
S3 0
S2 1
0 Set partial display duty ratio 0 0 Set N-line inversion 0 0 Release N-line inversion Reverse display ON/OFF 0 0
0 0 0 0 0 0 0
C6 1 D6 1 x 1 0
C5 0 D5 0 x 1 1
C4 0 D4 0 N4 0 0
C3 1 D3 1 N3 0 0
C2 0 D2 1 N2 1 1
Entire display ON/OFF
0
0
1
0
1
0
0
1
0
EON EON=0: normal display. EON=1: entire display ON
NOTE:
"x" is don't care.
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S6B1741
Table 16. Instruction Table (Continued)
Instruction Power control Select DC-DC step-up RS 0 0 RW 0 0 DB7 0 0 DB6 0 1 DB5 1 1 DB4 0 0 DB3 1 0 DB2 VC 1 DB1 VR DC1 DB0 VF DC0 Description Control power circuit operation Select the step-up of the internal voltage converter Select internal resistance ratio of the regulator resistor 2-byte instruction to specify the Reference voltage Select LCD bias COM bi-directional selection SHL=0: normal direction SHL=1: reverse direction ADC select 0 0 1 0 1 0 0 0 0 ADC SEG bi-directional selection ADC=0: normal direction ADC=1: reverse direction Oscillator on start Set power save mode 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 P Start the built-in oscillator P=0: normal mode P=1: sleep mode Release power save mode Initialize the internal functions 2-byte instruction to specify the number of data bytes. (SPI Mode) No operation Don't use this instruction.
Select regulator resistor
0
0
0
0
1
0
0
R2
R1
R0
Set electronic volume register Select LCD bias SHL select
0 0 0 0
0 0 0 0
1 x 0 1
0 x 1 1
0 EV5 0 0
0 EV4 1 0
0 EV3 0 SHL
0 EV2 B2 x
0 EV1 B1 x
1 EV0 B0 x
Release power save mode Reset Set data direction & display data length(DDL)
0 0 x x
0 0 x x 0 0
1 1 1
1 1 1
1 1 1
0 0 0
0 0 1
0 0 0
0 1 0
1 0 0
D7 1 1
D6 1 1
D5 1 1
D4 0 1
D3 0 x
D2 0 x
D1 1 x
D0 1 x
NOP Test Instruction NOTE: "x" is don't care.
0 0
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Table 16. Instruction Table (Continued)
Instruction Set FRC and PWM mode RS 0 RW 0 DB7 1 DB6 0 DB5 0 DB4 1 DB3 0 DB2 FRC DB1 PWM1 DB0 PWM0 Description FRC(1:3FRC, 0:4FRC) PWM1 PWM0 0 0 9PWM 0 1 9PWM 1 0 12PWM 1 1 15PWM Set white mode and 1st/2nd frame Set white mode and 3rd/4th frame Set light gray mode and 1st/2nd frame Set light gray mode and 3rd/4th frame Set dark gray mode and 1st/2nd frame Set dark gray mode and 3rd/4th frame Set black mode and 1st/2nd frame Set black mode and 3rd/4th frame
Set w hite mode and 1st/2nd frame, set pulse width Set white mode and 3rd/4th frame, set pulse width Set light gray mode and 1st/2nd frame, set pulse width Set light gray mode and 3rd/4th frame, set pulse width Set dark gray mode and 1st/2nd frame, set pulse width Set dark gray mode and 3rd/4th frame, set pulse width Set black mode and 1st/2nd frame, set pulse width Set black mode and 3rd/4th frame, set pulse width
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 WB3 1 WD3 1 LB3 1 LD3 1 DB3 1 DD3 1 BB3 1 BD3
0 WB2 0 WD2 0 LB2 0 LD2 0 DB2 0 DD2 0 BB2 0 BD2
0 WB1 0 WD1 0 LB1 0 LD1 0 DB1 0 DD1 0 BB1 0 BD1
0 WB0 0 WD0 0 LB0 0 LD0 0 DB0 0 DD0 0 BB0 0 BD0
1 WA3 1 WC3 1 LA3 1 LC3 1 DA3 1 DC3 1 BA3 1 BC3
0 WA2 0 WC2 0 LA2 0 LC2 1 DA2 1 DC2 1 BA2 1 BC2
0 WA1 0 WC1 1 LA1 1 LC1 0 DA1 0 DC1 1 BA1 1 BC1
0 WA0 1 WC0 0 LA0 1 LC0 0 DA0 1 DC0 0 BA0 1 BC0
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Read Display Data 8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display Data cannot be read through the serial interface. RS 1 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read Data
Write Display Data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write Data
Set Page Address Set Page Address Set Column Address Data write Column = Column + 1 YES Data Write Continue ? NO Optional Status YES Data Read Continue ? NO Optional Status Set Column Address Dummy Data Read Column = Column + 1 Data Read Column = Column + 1
Figure 27. Sequence for Writing Display Data
Figure 28. Sequence for Reading Display Data
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Read Status Indicates the internal status of the S6B1741 RS 0 RW 1 DB7 BUSY DB6 ON/OFF DB5 RES DB4 MF2 DB3 MF1 DB2 MF0 DB1 DS1 DB0 DS0
Flag BUSY
Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy Indicates display ON/OFF status 0: display OFF, 1: display ON Indicates the initialization is in progress by RESET signal. 0: chip is active, 1: chip is being reset Manufacturer ID, MF2 MF1 MF0 = [0 0 0] Display size ID, DS1 DS0 = [1 0]
ON/OFF RES MF DS
ICON Control Register ON/OFF This instruction makes ICON enable or disable. By default, ICON display is disabled (ICON= 0). When ICON control register is set to "1", ICON display is enabled and page address is set to "16". Then user can write data for icons. It is impossible to set the page address to "16" by Set Page Address instruction. Therefore, when writing data for icons, ICON control register ON instruction would be used to set the page address to "16". When ICON control register is set to "0", ICON display is disabled. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 ICON
ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16
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Set Page Address Sets the Page Address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address does not effect to the display status. Set Page Address instruction can not be used to set the page address to "16" . Use ICON control register ON/OFF instruction to set the page address to "16". RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 P3 DB2 P2 DB1 P1 DB0 P0
P3 0 0 : 1 1
P2 0 0 : 1 1
P1 0 0 : 1 1
P0 0 1 : 0 1
Page 0 1 : 14 15
Set Column Address Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased. Set Column Address MSB RS 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 Y7 DB1 Y6 DB0 Y5
Set Column Address LSB RS 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 Y4 DB2 Y3 DB1 Y2 DB0 Y1
Y7 0 0 : 1 1
Y6 0 0 : 1 1
Y5 0 0 : 1 1
Y4 0 0 : 1 1
Y3 0 0 : 1 1
Y2 0 0 : 1 1
Y1 0 1 : 0 1
Column address [Y7:Y1] 0 1 : 126 127
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Set Modify-Read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-Read instruction. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Reset Modify-Read This instruction cancels the Modify-Read mode, and makes the column address return to its initial value just before the set Modify-Read instruction is started. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
Set Page Address Set Column Address (N) Set Modify-Read Dummy Read Data Read Data Process Data Write
NO
Change Complete? YES Reset Modify-Read Return Column Address (N)
Figure 29. Sequence for Cursor Display
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S6B1741
Display ON/OFF Turns the display ON or OFF. This command has priority over Entire Display On/Off and Reverse Display On/Off. Commands are accepted while the display is off, but the visual state of the display does not change. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON
DON = 1: display ON DON = 0: display OFF Set Initial Display Line Register Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM display data is displayed at the top of row(COM0) of LCD panel. The 1s t Instruction RS 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 x DB0 x
The 2nd Instruction RS 0 S6 0 0 0 0 : 1 1 1 1 RW 0 S5 0 0 0 0 : 1 1 1 1 DB7 x S4 0 0 0 0 : 1 1 1 1 DB6 S6 S3 0 0 0 0 : 1 1 1 1 DB5 S5 S2 0 0 0 0 : 1 1 1 1 S1 0 0 1 1 : 0 0 1 1 DB4 S4 S0 0 1 0 1 : 0 1 0 1 DB3 S3 DB2 S2 DB1 S1 Line address 0 1 2 3 : 124 125 126 127 DB0 S0
Setting Initial Display Line Start
1 s t Instruction (2-byte Instruction for Mode Setting)
2nd Instruction (2-byte Instruction for Register Setting)
Setting Iinitial Display Line End
Figure 30. The Sequence for Setting the Initial Display Line
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Set Initial COM0 Register Sets the initial row (COM0) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the window moving without the change of display data. The 1s t Instruction RS 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 1 DB1 x DB0 x
The 2nd Instruction RS 0 RW 0 DB7 x DB6 C6 DB5 C5 DB4 C4 DB3 C3 DB2 C2 DB1 C1 DB0 C0
C6 0 0 0 0 : 1 1 1 1
C5 0 0 0 0 : 1 1 1 1
C4 0 0 0 0 : 1 1 1 1
C3 0 0 0 0 : 1 1 1 1
C2 0 0 0 0 : 1 1 1 1
C1 0 0 1 1 : 0 0 1 1
C0 0 1 0 1 : 0 1 0 1
Initial COM0 COM0 COM1 COM2 COM3 : COM124 COM125 COM126 COM127
Setting Initial COM0 Start
1s t Instruction (Mode Setting)
2nd Instruction (Initial COM0 Setting)
Setting Iinitial COM0 End
Figure 31. Sequence for Setting the Initial COM0
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Set Partial Display Duty Ratio Sets the duty ratio within range of 16 to 128 (ICON disabled) or 17 to 129 (ICON enabled) to realize partial display by using the 2-byte instruction. The 1s t Instruction RS 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 x DB0 x
The 2nd Instruction RS 0 RW 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
D7 0 : 0 0 0 : 0 1 1 : 1
D6 0 : 0 0 0 : 1 0 0 : 1
D5 0 : 0 0 0 : 1 0 0 : 1
D4 0 : 0 1 1 : 1 0 0 : 1
D3 0 : 1 0 0 : 1 0 0 : 1
D2 0 : 1 0 0 : 1 0 0 : 1
D1 0 : 1 0 0 : 1 0 0 : 1
D0 0 : 1 0 1 : 1 0 1 : 1
Selected Partial Duty Ratio (ICON Disabled) No operation
Selected Partial Duty Ratio (ICON Enabled) No operation
1/16 1/17 : 1/127 1/128 No operation
1/17 1/18 : 1/128 1/129 No operation
Setting Initial Display Start
1s t Instruction (Mode Setting)
2 nd Instruction (Partial Display Duty Setting)
Setting Partial Display End
Figure 32. Sequence for Setting Partial Display
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Set N-line Inversion Register Sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal LCD AC signal (M) by using the 2-byte instruction. The DC-bias problem could be occurred if K is even number. So, we recommend customers to set K to be odd number. K : D/N D : The number of display duty ratio (D is selectable by customers) N : N for N-line inversion (N is selectable by customers). The 1s t Instruction RS 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 1 DB1 x DB0 x
The 2nd Instruction RS 0 RW 0 DB7 x DB6 x DB5 x DB4 N4 DB3 N3 DB2 N2 DB1 N1 DB0 N0
N4 0 0 0 0 : 1 1 1
N3 0 0 0 0 : 1 1 1
N2 0 0 0 0 : 1 1 1
N1 0 0 1 1 : 0 1 1
N0 0 1 0 1 : 1 0 1
Selected n-line inversion 0-line inversion (frame inversion) 3-line inversion 4-line inversion 5-line inversion : 31-line inversion 32-line inversion 33-line inversion
Setting N-Line Inversion Start
1s t Instruction (Mode Setting)
2nd Instruction (N-Line Inversion Setting)
Setting N-Line Inversion End
Figure 33. Sequence for N-line Inversion
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Release N-line Inversion Returns to the frame inversion condition from the n-line inversion condition. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
Reverse Display ON/OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
REV 0 (normal) 1 (reverse)
DDRAM data = "00" - White White ("00") Dark ("11")
DDRAM data = "01" - Light gray Light gray ("01") Dark gray ("10")
DDRAM data = "10" - Dark gray Dark gray ("10") Light gray ("01")
DDRAM data = "11" - Dark Dark ("11") White ("00")
Entire Display ON/OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display ON/OFF instruction. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON
EON 0 (normal) 1 (entire)
DDRAM data = "00" - White White ("00") Dark ("11")
DDRAM data = "01" - Light gray Light gray ("01") Dark gray ("11")
DDRAM data = "10" - Dark gray Dark gray ("10") Light gray ("11")
DDRAM data = "11" - Dark Dark ("11") White ("11")
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Power Control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
VC 0 1
VR
VF
Status of internal power supply circuits Internal voltage converter circuit is OFF. Internal voltage converter circuit is ON.
0 1 0 1 Select DC-DC Step-up
Internal voltage regulator circuit is OFF. Internal voltage regulator circuit is ON. Internal voltage follower circuit is OFF. Internal voltage follower circuit is ON.
Selects one of 4 DC-DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial display function. RS 0 RW 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 DC1 DB0 DC0
DC1 0 0 1 1
DC0 0 1 0 1
Selected DC-DC converter circuit 3 times boosting circuit 4 times boosting circuit 5 times boosting circuit 6 times boosting circuit
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
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Select Regulator Resistor Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 0 DB2 R2 DB1 R1 DB0 R0
R2 0 0 0 0 1 1 1 1
R1 0 0 1 1 0 0 1 1
R0 0 1 0 1 0 1 0 1
1+ (Rb/Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Set Electronic Volume Register Consist of 2-byte Instructions The 1st instruction set Reference Voltage mode, the 2nd one updates the contents of reference voltage register. After second instruction, Reference Voltage mode is released. The 1s t Instruction: Set Reference Voltage Select Mode RS 0 RW 0 DB7 1 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
The 2nd Instruction: Set Reference Voltage Register RS 0 RW 0 DB7 x DB6 x DB5 EV5 DB4 EV4 DB3 EV3 DB2 EV2 DB1 EV1 DB0 EV0
EV5 0 0 : : 1 1
EV4 0 0 : : 1 1
EV3 0 0 : : 1 1
EV2 0 0 : : 1 1
EV1 0 0 : : 1 1
EV0 0 1 : : 0 1
Reference voltage parameter () 0 1 : : 62 63
Setting Reference Voltage Start
1 s t Instruction for Mode Setting
2nd Instruction for Register Setting
Setting Reference Voltage End
Figure 34. Sequence for Setting the Electronic Volume
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Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 B2 DB1 B1 DB0 B0
B2 0 0 0 0 1 1 1 1 SHL Select
B1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1
LCD bias 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12
COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x x : Don't care SHL = 0: normal direction (COM0 COM127) SHL = 1: reverse direction (COM127 COM0) ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins could be reversed by software. This makes IC layout flexible in LCD module assembly. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
ADC = 0: normal direction (SEG0 SEG127) ADC = 1: reverse direction (SEG127 SEG0)
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Oscillator ON Start This instruction enables the built-in oscillator circuit. RS 0 Power Save The S6B1741 enters the Power Save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. Set Power Save Mode RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 P RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
P = 0: normal mode P = 1: sleep mode Release Power Save Mode RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Set Power Save Mode (Sleep Mode)
Sleep Mode Oscillator Circuits: OFF LCD Power Supply Circuits: OFF All COM / SEG Output Level: V SS Consumption Current < 2uA
Release Power Save Mode (Sleep Mode)
Figure 35. Power Save Routine
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Reset This instruction Resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
Set Data Direction & Display Data Length (3-Pin SPI Mode) Consists of 2 bytes instruction. This command is used in 3-Pin SPI mode only(PS0 = "L" and PS1 = "L"). It will be two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second byte will be number of data bytes will be write. When RS is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. The 1s t Instruction: Set Data Direction (Only Write Mode) RS x RW x DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 0
The 2nd Instruction: Set Display Data Length (DDL) Register RS x RW x DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
D7 0 0 0 : 1 1 1
D6 0 0 0 : 1 1 1
D5 0 0 0 : 1 1 1
D4 0 0 0 : 1 1 1
D3 0 0 0 : 1 1 1
D2 0 0 0 : 1 1 1
D1 0 0 1 : 0 1 1
D0 0 1 0 : 1 0 1
Display Data Length 1 2 3 : 254 255 256
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
NOP No operations RS 0 Test Instruction This instruction is for testing IC. Please do not use it. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
Set PWM & FRC mode Selects 3/4 FRC and 9/12/15 PWM RS 0 RW 0 DB7 1 DB6 0 DB5 0 DB4 1 DB3 0 DB2 FRC DB1 PWM1 DB0 PWM0
FRC 0 1
PWM1
PWM0
Status of PWM & FRC 4FRC 3FRC
0 0 1 1
0 1 0 1
9PWM 9PWM 12PWM 15PWM
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Set Gray Scale Mode & Register Consists of 2 bytes instruction. The first byte sets grayscale mode and the second byte updates the contents of gray scale register without issuing any other instruction. Set Gray Scale Mode RS 0 RW 0 DB7 1 DB6 0 DB5 0 DB4 0 DB3 1 DB2 GM2 DB1 GM1 DB0 GM0
GM2 0 0 0 0 1 1 1 1
GM1 0 0 1 1 0 0 1 1
GM0 0 1 0 1 0 1 0 1
Description In case of setting white mode and 1st/2nd frame. In case of setting white mode and 3rd/4th frame. In case of setting light gray mode and 1st/2nd frame. In case of setting light gray mode and 3rd/4th frame. In case of setting dark gray mode and 1st/2nd frame. In case of setting dark gray mode and 3rd/4th frame. In case of setting black mode and 1st/2nd frame. In case of setting black mode and 3rd/4th frame.
Set Gray Scale Register RS 0 0 RW 0 0 DB7 GB3 GD3 DB6 GB2 GD2 DB5 GB1 GD1 DB4 GB0 GD0 DB3 GA3 GC3 DB2 GA2 GC2 DB1 GA1 GC1 DB0 GA0 GC0
GA3, GB3, GC3, GD3 0 0 : 1 1 1 1 1 1 1
NOTE:
GA2, GB2, GC2, GD2 0 0 : 0 0 0 1 1 1 1
GA1, GB1, GC1, GD1 0 0 : 0 1 1 0 0 1 1
GA0, GB0, GC0, GD0 0 1 : 1 0 1 0 1 0 1
Pulse width (9PWM) 0/9 1/9 : 9/9 0/9 0/9 0/9 0/9 0/9 0/9
Pulse width (12PWM) 0/12 1/12 : 9/12 10/12 11/12 12/12 0/12 0/12 0/12
Pulse width (15PWM) 0/15 1/15 : 9/15 10/15 11/15 12/15 13/15 14/15 15/15
GA3=WA3,LA3,DA3,BA3 GA2=WA2,LA2,DA2,BA2 GA1=WA1,LA1,DA1,BA1 GA0=WA0,LA0,DA0,BA0 GB3=WB3,LB3,DB3,BB3 GA2=WB2,LB2,DB2,BB2 GA1=WB1,LB1,DB1,BB1 GA0=WB0,LB0,DB0,BB0 GC3=WC3,LC3,DC3,BC3 GA2=WC2,LC2,DC2,BC2 GA1=WC1,LC1,DC1,BC1 GA0=WC0,LC0,DC0,BC0 GD3=WD3,LD3,DD3,BD3 GA2=WD2,LD2,DD2,BD2 GA1=WD1,LD1,DD1,BD1 GA0=WD0,LD0,DD0,BD0
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Referential Instruction Set-up Flow: Initializing with the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON (VDD-VSS) with keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select]
Set the LCD Operating Voltage by Internal Instructions [Oscillator on start] [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Gray-scale Select]
Turn On the Voltage Converter by Internal Instructions [Power Control: VC=1, VR=0, VF=0] Wating for 50% rising of VOUT Turn On the Voltage Regulator by Internal Instructions [Power Control: VC=1, VR=1, VF=0] Waiting for 1ms Turn On the Voltage Follower by Internal Instructions [Power Control: VC=1, VR=1, VF=1]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 36. Initializing with the Built-in Power Supply Circuits
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
Referential Instruction Set-up Flow: Initializing without the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON (VDD-VSS) with keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
Set Power Save
User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register select]
Set the LCD Operating Voltage by Internal Instructions [Oscillator ON] [Regulator or Flower Register Select] [Gray-Scale Select] [Power Control]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 37. Initializing without the Built-in Power Supply Circuits
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Set-up Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Initial Display Data by Instruction [Display Data Write]
Turn Display ON by Instruction [Display On/Off: DON=1]
End of Data Display
Figure 38. Data Displaying
Referential Instruction Set-up Flow: Power OFF
Optional Status
Set Power Save by Instruction
Power OFF (VDD-VSS)
End of Power OFF
Figure 39. Power OFF
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
Referential Instruction Set-up Flow: Partial Duty Changing
Start of Partial Changing
Set Display OFF by Internal [Display ON/OFF: DON=0]
Set Sleep Mode by Internal Instructions [Power Save Mode]
Set Partial Duty by Internal Instructions [Partial Display Duty Ratio Select] [Initial Display Line Register] [COM0 Register Select]
Set the LCD Operating Voltage for Partial Display by Internal Instructions [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Gray-scale Select]
Waiting for Discharging the LCD Power Levels
Release Power Save
Waiting for Stabilizing the LCD Power Levels
Write Display Data & Display ON by Internal Instruction [Display Data Write] [Display ON/OFF: DON=1]
End of Partial Changing
Figure 40. Partial Duty Changing
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS Table 17. Absolute Maximum Ratings (V SS = 0V) Parameter Supply voltage range Symbol VDD V0, VOUT V1, V2, V3, V4 External reference voltage Input voltage range Operating temperature range Storage temperature range VEXT VIN TOPR TSTR Rating - 0.3 to + 7.0 - 0.3 to + 17.0 - 0.3 to V0 + 0.3 +0.3 to VDD - 0.3 to VDD + 0.3 - 40 to + 85 - 55 to + 125 Unit V V V V V C C
NOTES: 1. VDD, V0, VOUT, V1 to V4 and VEXT are based on VSS = 0V. 2. Voltages V0 V1 V2 V3 V4 VSS must always be satisfied.(VLCD = V0 - VSS) 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
DC CHARACTERISTICS Table 18. DC Characteristics (V SS = 0V, VDD = 1.8 to 3.3V, Ta = -40 to 85C) Item Operating Voltage (1) Operating Voltage (2) Input Voltage High Low Output Voltage High Low Symbol VDD V0 VIH VIL VOH VOL IIL IOZ RON fOSC VCI IOH = -0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS Ta = 25C, V0 = 8V Ta = 25C (*11) x3 x4 x5 x6 Voltage Converter Output Voltage Voltage Regulator Operating Voltage Voltage Follower Operating Voltage Reference Voltage VOUT x3/x4/x5/x6 voltage conversion (no-load ) Condition Min. 1.8 4.0 0.8V DD VSS 0.8V DD VSS - 1.0 - 3.0 1.8 1.8 1.8 1.8 95 Typ. 2.0 99 Max. 3.3 15.0 VDD 0.2V DD VDD 0.2V DD + 1.0 + 3.0 3.0 900 3.6 3.6 3.0 2.5 % VOUT A A k KHz V
(3) (5)
Unit V V V
Pin used VDD (1) V0 (2)
(3)
V
(4)
Input Leakage Current Output Leakage Current LCD Driver ON Resistance Operating frequency Voltage Converter Input Voltage
SEGn COMn (6) (*7) (*11) VCI
VOUT V0 VREF Ta = 25C
5.4 4.0 2.04
2.10
15.0 15.0 2.16
V V V
VOUT V0 (8)
(9)
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Dynamic Current Consumption when The Internal Power Supply is ON Table 19. Dynamic Current 2 (Internal Power) (V DD = 3.0V, Ta = 25C) Item Dynamic Current Consumption Symbol IDD Condition V0 - VSS = 12.0V, x5 boosting, duty = 1/128, normal mode (Display Off) V0 - VSS = 12.0V, x5 boosting, duty = 1/128, normal mode (Display On , Checker Pattern) Min. Typ. 100 Max. 150 Unit A Pin used
(10)
-
200
300
A
(10)
Current Consumption during Power Save Mode Table 20. Power Save Mode Current (V DD = 3.0V, Ta = 25C) Item Sleep Mode Current Symbol IDDS1 Condition During Sleep Min. Typ. Max. 2 Unit A Pin used
(10)
Table 21. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio 1/N Item On-chip oscillator circuit is used fCL fOSC
fFR
xN
fFR
x PWM x 2 x N
(fOSC: oscillation frequency, fCL: display clock frequency, fFR: frame frequency, N = 16 to 129)
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
NOTES: 1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. 2. In case of external power supply is applied. 3. CSB, RS, DB0 to DB7, E_RD, RW_WR, RESETB, PS1, PS0, INTRS and REF 4. DB0 to DB7 5. Applies when the DB0 to DB7 pins are in high impedance. 6. Resistance value when -0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON [k] = V[V]/0.1[mA] (V : voltage change when -0.1[mA] is applied in the ON status.) 7. See Table 22 for the relationship between oscillation frequency and frame frequency. 8. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. 9. On-chip reference voltage source of the voltage regulator circuit to adjust V0. 10. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON. The current flowing through voltage regulation resistors(Rb and Ra) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc. The other conditions are 1/12 bias, 3 FRC, 9 PWM, Frame inversion, Frame freq. = 85HZ, BL=(9,9,9,0), DG=(6,6,6,0), LG=(3,3,3,0), WH=(0,0,0,0). 11. REXT = 620k applies when PWM method is used.
When both PWM and FRC method are used, frame frequency should be increased up to more than`50Hz x n' (n: Used FRC number). So, oscillator resistor value between OSC1 and VDD pin should be reduced.
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS Read/Write Characteristics (8080-series MPU)
RS tAS80 t CY80 tPWL /RD, /WR CSB DB0 to DB7 (Write) tACC80 DB0 to DB7 (Read) tOD80 0.9VDD 0.1VDD tDS80 tDH80 t PWH tAH80
Figure 41. Read/Write Characteristics (8080-series MPU) (V DD = 1.8V, Ta = -40 to +85C) Item Address Setup Time Address Hold Time System Cycle Time For Write System Cycle Time For Read Pulse Width Low Pulse Width High Data Setup Time Data Hold Time Read Access Time Output Disable Time /WR /RD DB0-DB7 Signal RS Symbol tAS80 tAH80 tCY80 tCY80 tPWL tPWH tDS80 tDH80 tACC80 tOD80 CL = 100 pF Condition Min. 0 0 150 330 60 60 40 10 15 10 Max. 50 Unit ns ns ns ns ns
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
(V DD = 2.7V, Ta = -40 to +85C) Item Address Setup Time Address Hold Time System Cycle Time For Write System Cycle Time For Read Pulse Width Low Pulse Width High Data Setup Time Data Hold Time Read Access Time Output Disable Time
NOTE:
Signal RS
Symbol tAS80 tAH80 tCY80 tCY80
Condition
Min. 0 0 100 166 40 40 30 5
Max. 50
Unit ns ns ns ns ns
/WR /RD DB0-DB 7
tPWL tPWH tDS80 tDH80 tACC80 tOD80 CL = 100 pF
15 10
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read.
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Read/Write Characteristics (6800-series Microprocessor)
RS RW tAS68 tCY68 tEWL CSB 0.9VDD 0.1VDD tEWL E 0.1VDD 0.9V DD tEWH tDS68 DB0 to DB7 (Write) tACC68 DB0 to DB7 (Read) tOD68 tDH68 tEWH tAH68
Figure 42. Read/Write Characteristics (6800-series Microprocessor) (V DD = 1.8V, Ta = -40 to +85C) Item Address Setup Time Address Hold Time System Cycle Time For Write System Cycle Time For Read Enable Width High Enable Width Low Data Setup Time Data Hold Time Read Access Time Output Disable Time E_RD (E) DB0 to DB7 Signal RS RW_WR Symbol tAS68 tAH68 tCY68 tCY68 tEWH tEWL tDS68 tDH68 tACC68 tOD68 CL = 100 pF Condition Min. 0 0 150 330 60 60 40 10 15 10 Max. 50 Unit ns ns ns ns
ns
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
(V DD = 2.7V, Ta = -40 to +85C) Item Address Setup Time Address Hold Time System Cycle Time For Write System Cycle Time For Read Enable Width High Enable Width Low Data Setup Time Data Hold Time Read Access Time Output Disable Time
NOTE:
Signal RS RW_WR
Symbol tAS68 tAH68 tCY68 tCY68
Condition
Min. 0 0 100 166 40 40 30 5
Max. 50
Unit ns ns ns ns ns
E_RD (E) DB0DB7
tEWH tEWL tDS68 tDH68 tACC68 tOD68 CL = 100 pF
15 10
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (t CY68 - tEWHW - tEWLW ) for write, (tr + tf) < (t CY68 - tEWHR - tEWLR ) for read.
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
Serial Interface Characteristics
tCSS CSB tASS RS tAHS
tCHS
tCYS DB6 (SCLK) 0.9VDD 0.1VDD tWLS tDSS DB7 (SID) tWHS tDHS
Figure 43. Serial Interface Characteristics (V DD = 1.8V, Ta = -40 to +85C) Item Serial Clock Cycle SCLK High Pulse Width SCLK Low Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CSB Setup Time CSB Hold Time Signal DB6 (SCLK) Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS Condition Min. 111 60 60 60 60 60 60 60 1/2 * tCYS Max. Unit ns
RS DB7 (SID) CSB
ns ns ns
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
(V DD = 2.7V, Ta = -40 to +85C) Item Serial Clock Cycle SCLK High Pulse Width SCLK Low Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CSB Setup Time CSB Hold Time
NOTE:
Signal DB6 (SCLK)
Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS
Condition
Min. 58.8 30 30 30 30 30 30 30 1/2 * tCYS
Max. -
Unit ns
RS DB7 (SID) CSB
ns ns ns
The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Reset Input Timing
tRW RESETB Internal Status During Reset
tR Reset Complete
Figure 44. Reset Input Timing (V DD = 1.8 to 3.3V, Ta = -40 to +85C) Item Reset Low Pulse Width Reset Time Signal RESETB Symbol tRW tR Condition Min. 1000 Max. 1000 Unit ns ns
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE In Case of Interfacing with 6800-series (PS0 = "H", PS1 = "H")
CSB RS E 6800-series MPU RW DB0 to DB7 RESETB VDD VDD
CSB RS E_RD RW_WR DB0 to DB7 RESETB PS0 PS1 S6B0741
Figure 45. Interfacing with 6800-series (PS0 = "H", PS1 = "H")
In Case of Interfacing with 8080-series (PS0 = "H", PS1 = "L")
CSB RS /RD 8080-series MPU /WR DB0 to DB7 RESETB VDD VSS
CSB RS E_RD RW_WR DB0 to DB7 RESETB PS0 PS1 S6B0741
Figure 46. Interfacing with 8080-series (PS0 = "H", PS1 = "L")
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128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
S6B1741
In Case of 4-pin SPI mode (PS0 = "L" , PS1 = "H" )
CSB RS SID MPU SCLK RESETB OPEN VSS VDD
CSB RS DB7(SID) DB6(SCLK) RESETB DB0 to DB6 PS0 PS1 S6B0741
Figure 47. Serial Interface (PS0 = "L" , PS1 = "H" )
In Case of 3-pin SPI mode (PS0 = "L" , PS1 = "L" )
CSB SID SCLK MPU RESETB OPEN
CSB DB7(SID) DB6(SCLK) RESETB DB0 to DB6 S6B0741
VSS VSS
PS0 PS1
Figure 48. Serial Interface (PS0 = "L" , PS1 = "L" )
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S6B1741
128SEG/129COM DRIVER & CONTROLLER FOR STN LCD
CONNECTIONS BETWEEN S6B1741 AND LCD PANEL Single Chip Configuration (1/129 Duty Configurations)
COMS COM127 : COM64 SEG127
S6B0741 (Bottom View)
COM63 : COM0 COMS SEG0
COM63 : COM0 COMS SEG0
S6B0741 (TOP View)
COMS COM127 : COM64

(R)

(R)
129 x 128 pixels
(R)
129 x 128 pixels
(R)
Figure 49. SHL = 0, ADC = 1
Figure 50. SHL = 0, ADC = 0

(R)

(R)
129 x 128 pixels
(R)
129 x 128 pixels
(R)
SEG0 COMS COM0 : COM63
SEG127
S6B0741 (Bottom View)
COM64 : COM127 COMS
COM64 : COM127 COMS
S6B0741 (TOP View)
COMS COM0 : COM63
Figure 51. SHL = 1, ADC = 0
Figure 52. SHL = 1, ADC = 1
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